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SCG102A Synchronous Clock Generators
PLL
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Applications
* SONET / SDH / ATM * DWDM / FDM * DSL-PON Interconnects * FEC (Forward Error Correction)
Features
* 3.3V High Precision PLL * Accepts 1 of 4 Selectable, Pre-determined Input Frequencies * 77.76 MHz to 170 MHz Output Frequencies Available. * Jitter Generation OC-192 Compliant * 1.0" x 0.80" x 0.285", Surface Mount
Bulletin Page Revision Date Issued By
SG076 1 of 8 00 11 APR 07 ENG
General Description
The SCG102A provides high precision phase lock loop frequency translation for the telecommunication applications. The SCG102A product generates LVPECL outputs from an intrinsically low jitter, voltage controlled crystal oscillator. SCG102A is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment . The SCG102A provides a jitter filtered, wander following output signal sychronized to a superior Stratum or peer input reference signal. The SCG102A includes a lock detect alarm output. The PLL control voltage is brought out through a 470 k restistor and can be used to determine when the pull range limits are reached.The LVPECL outputs may be put into the tri-state high impedance condition for external testing purposes by asserting a high signal to the Enable/Disable pin. The SCG102A is a 3.3 Volt component that will typically draw 75mA. The SCG102A is designed to be used in applications that require temperature rating of -40C - 85 C. The SCG102A package typical dimensions are 1.0" x 0.80" x 0.285" (See fig. 2 for maximum dimensions). Parts are assembled using high temperature solder to withstand surface mount reflow process. The SCG102A locks to any one of four pred-determined input frequencies selected using the SELECT (A&B) lines (See Table 4). The output may be any single frequency from 77.76 MHz to 170 MHZ.
Functional Block Diagram
Figure 1
LD
470 k (Pin 3)
Monitor
(Pin 4)
CLKIN
(Pin 1)
Frequency Divider
Loop Filter
PECL VCXO
OUT
(Pin 9)
COut
(Pin 10)
Frequency
10 k
Divider
Select A
(Pin 12)
Microprocessor
10 k
Select B
(Pin 13)
Enable/Disable
(Pin 8)
Absolute Maximum Rating
Table 1
Symbol Vcc VI Ts Parameter Power Supply Voltage Input Voltage Storage Temperature Minimum -0.3 -0.3 -55 Nominal Maximum 5.5 Vcc 125 Units Volts Volts C Notes
Data Sheet #: SG076
Page 2 of 8
Rev: 00
Date: 4/11/07
(c) Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Specifications
Table 2
Symbol fIN fOUT Vcc ICC CLKIN CLKOUT VOH VOL TR/TF SYM BW JGEN JTRAN APR TOP
NOTES:
Parameter Available Input Frequencies CMOS PECL Output Frequencies(LVPECL) Supply Voltage Supply Current Input Logic A = CMOS D = PECL
Minimum 8k 1M 77.76 M 3.135
Nominal
Maximum 100 M 100 M 170 M
Units Hz Hz Hz Volts mA
Notes
3.3 75 CMOS PECL PECL
3.465 100
1
Output Logic F = Comp. PECL 2.275
V 1.68 V ns % Hz 1 0.1 ps dB ppm 85 70 C C 2 0.5 1 55 20 0.5
Rise/Fall Time Output Symmetry Bandwidth Jitter Generation RMS (12 kHz - 20 MHz) Jitter Transfer Input Frequency Tracking Operating Temperature F= C= 50 -40 0 45
1.0: Only HCMOS and LVHCMOS is supported for input frequencies < 1MHz 2.0: GR-253-CORE, Sec. 5.6.2.1.2
Pin Description
Table 3
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Connection CLKIN GND Lock Detector VCXO Monitor ---NC GND Enable/Disable Out COut NC Select A Select B NC GND VCC Description Input Frequency - The SCG102A AC couples the input , this means that the unit is capable of handling HCMOS, LVCMOS, PECL, LVPECL input signals. Ground Logic "1" indicates that the unit is locked to the input reference Logic "0" indicates that the reference is lost or out of lock range Control voltage level for the PECL oscillator (Between 0.3V and 3.0V when locked) Missing No connection Ground Logic "0" (or no connect) = Output Enabled Logic "1" = Output Disabled (Tri-Stated) Output Complementary Output No connection Input Frequency Select Control Pin. See Table 4. Input Frequency Select Control Pin. See Table 4. No connection Ground Power supply voltage (3.3 Vdc 5%)
Data Sheet #: SG076
Page 3 of 8
Rev: 00
Date: 4/11/07
(c) Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Input Frequency Selection
Table 4
Input Freq f1 f2 f3 f4
SEL A 0 0 1 1
SEL B 0 1 0 1
Output Load and Power Supply Filtering Recommendations
Figure 2
*
*
*
* It is highly recommended
that either a linear regulator or bypass capacitors be used. Typical values would be 10 uF, 0.1 uF, 100 pF.
VT -2 VDC LD
(Pin 3) 470 k
Monitor
(Pin 4)
50
50
CLKIN
(Pin 1)
Frequency Divider
Loop Filter
PECL VCXO
OUT
(Pin 9)
COut
(Pin 10)
(FOUT)
Frequency
10 k
Divider
Select A
(Pin 12)
Microprocessor
10 k
Select B
(Pin 13)
Enable/Disable
(Pin 8)
Data Sheet #: SG076
Page 4 of 8
Rev: 00
Date: 4/11/07
(c) Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Ordering Information
Table 5
10 MHz 10 kHz 8 kHz 16 kHz 64 kHz 1.024 MHz 1.048 MHz 1.544 MHz 2.048 MHz 4.096 MHz A B C D E F G H J K 8.192 MHz 13.00 MHz 16.384 MHz 19.44 MHz 20.48 MHz 26.00 MHz 27.00 MHz 38.88 MHz 44.736 MHz 53.10468 MHz L M N P R T W X Y Z 51.84 MHz 61.44 MHz 77.76 MHz 82.944 MHz 112.00 MHz 139.264 MHz 155.52 MHz 166.6286 MHz 114.0 MHz 125.0 MHz 0 1 2 3 4 5 6 7 8 9
For any model, the reference inputs and output frequency must have a common frequency of 2.667Hz (8kHz/3) Ex 1: A Model with reference inputs of 8kHz, 16kHz, 32kHz and 64kHz with a Output frequency of 155.52MHz is valid due to the common frequency of 2.667kHz. Contact CW regarding models that do not have a input/output common frequency of 2.667kHz.
SCG102A- D F F - A 1 P 6
Supply Voltage D = 3.3 VDC 5%
Output Type F = Comp. PECL
Temperature Range C = 0C to 70C F = -40C to 85C
Output Frequency (2 to 9) See chart above. If a custom frequency is desired, enter S followed by the frequency. Contact a sales representative for the availabilty of custom frequencies. Input Frequency (A to 9) See chart above. If more than one frequency is desired, enter S and list all desired frequencies. Contact a sales representative for the availabilty of custom frequencies. Number of Input Frequencies 1 = 1 Input Frequency 2 = 2 Input Frequencies 3 = 3 Input Frequencies 4 = 4 Input Frequencies
Sample Part Number Examples: SCG-102A- DFF-A1C2 SCG-102A- DFF-A4S2, S = 8 kHz, 16.384 MHz, 19.44 MHz, 38.88 MHz SCG-102A-DFF-D1ZS, S = Custom Frequency
Input Logic A = CMOS D = PECL
Data Sheet #: SG076
Page 5 of 8
Rev: 00
Date: 4/11/07
(c) Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Package Dimensions
Figure 3
Recommended Footprint Dimensions
Figure 4
.100 [2.54mm]
1.000 [25.40mm]
PIN 1 .740 [18.80mm] .285 [7.24mm] MAX.
.800 [20.32mm]
Solder Profile
Figure 5
300
250
Peak Temp. 245-255C for 15 sec Typ.
221C 200
Temp (C)
150 Soaking Zone 60-90 sec Typ. (2 min Max) 100
Reflow Zone 30/90 sec (Min/Max)
50
Ramp Slope not to exceed 3C/sec
0 0 50 100 150 Time (sec) 200 250 300 350
Data Sheet #: SG076
Page 6 of 8
Rev: 00
Date: 4/11/07
(c) Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG076
Page 7 of 8
Rev: 00
Date: 4/11/07
(c) Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Revision 00
Revision Date 4/11/07
Note Final Release

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